Srinivasa R. Vemuru

 

Mailing Address:

Professor, Department of Electrical and Computer Engineering and Computer Science
Ohio Northern University,  Ada OH 45810

Office:  Biggs 245

Tel: (419) 772-2388

FAX :  (419) 772-2404

E-mail: s-vemuru@onu.edu

Education:  

Ph.D., Electrical Engineering, The University of Toledo ,Toledo, Ohio, 1991
M.Tech., Electrical Engineering, Indian Institute of Technology, Madras, India, 1986
B.Tech., Electrical Engineering, Indian Institute of Technology , Madras, India, 1984

Research Interests:

Analog phenomena in digital circuits, analog and digital circuit design, CAD for VLSI, VLSI testing.

Recent Publications:

A. N. Elkammar, S. R. Vemuru and N. Scheinberg, " Bus Encoding Scheme to Eliminate Unwanted Signal Transistions" , Proceedings of Third IEEE International Workshop on Electronic Design, Test & Applications, DELTA 2006, Kaula Lumpur, Malaysia, Jan 17-19, 2006.
M. Niamat, A. Ravinuthala, and S. Vemuru, "BIST for embedded SRAMs in Systems on Chips",  Proceedings of  International Conference on Embedded Systems and Applications, ESA'05, Las Vegas, June 2005, pp. 74-80.

A. N. Elkammar, S. R. Vemuru and N. Scheinberg, " A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions" , Proceedings of  International Conference on Embedded Systems and Applications, ESA'04, Las Vegas, June 2004, pp. 12-17.
S. R. Vemuru, " Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitances
", International Conference on VLSI , VLSI'03 , Las Vegas, June, 2003.
Nathaniel Bird, Ethan Miller, Paul Pfeiffer and Srinivasa Vemuru, "Channel Routing with Crosstalk Considerations",
Proceedings of the International Conference on VLSI , VLSI'03 , Las Vegas, June, 2003, pp. 119-124.
S. R. Vemuru and A. N. Elkammar, "Scaling of serially connected MOS transistors with constant area constraint,'' in the Proceedings of the  IEEE  Midwest Symposium on Circuits and Systems , Tulsa, OK, August 2002. 
S. R. Vemuru and O. Ogunnika, ``Dual-modulus prescalar implementation using clock suppression'' Proceedings of the International Conference on VLSI, VLSI'02 , Las Vegas, June, 2002, pp. 102-106. 
S. R. Vemuru, ``Effects of simultaneous switching noise on tapered buffer design,'' IEEE Transactions on VLSI Systems , vol. 5, no. 3, pp. 290-300, September, 1997. 
S. R. Vemuru, ``Accurate simultaneous switching noise estimation including velocity saturation effects,'' IEEE Transactions on Components, Hybrids, and Packaging-Part B: Advanced Packaging , vol 19, no. 2, pp. 344-349, May 1996. 
S. R. Vemuru, ``Delay-macromodeling of CMOS transmission-gate-based circuits,'' International Journal of Modelling and Simulation, vol 15., no. 3, pp. 90-97, June 1995. 
S. R. Vemuru, ``Split inherent-capacitive load model for CMOS buffer design,'' International Journal of Electronics , vol. 78, no. 2, pp. 359-365, February 1995. 
S. R. Vemuru and N. Scheinberg, ``Short-circuit power dissipation estimation for CMOS logic gates,'' IEEE Transactions on Circuits and Systems - Part I , vol. 41, no. 11, pp. 762-765, November 1994.

Course Notes:

ECCS 261, Digital Electronics

ECCS 2721: Digital Logic

ECCS 362, Microprocessors

ECCS 363, Advanced Digital Electronics

ECCS 365, Computer Architecture

ECE 467, Computer Device Lab (Computer Systems)
 
ECCS 3241: Embedded Systems (Computer Systems)  
 

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